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Jun 12, 2018 FrontPanel Driver - Use the DriverOnly installer and run this installer during your application installation process. Microsoft Visual Studio C Redistributable (for FrontPanel) - Install and run this redistributable package. Note that the bitness of this must match the bitness of the FrontPanel Library. The light came on when I saw the Opal Kelly product line - it was perfect for us. It has memory, USB, powerful FPGA with lots of I/O, and not much else. This is a fundamental value of Opal Kelly modules - they have the minimum configuration to be incredibly flexible and useful, without the cost and complexity of unnecessary accessories. With integrated SDRAM, power supplies, and platform flash, the XEM6310 is a worthy addition to Opal Kelly’s most popular form-factor. FrontPanel™ SDK. Opal Kelly’s FrontPanel SDK is an easy-to-use, robust API for communication, configuration, and interfacing to your PC, Mac or Linux hardware. Apr 27, 2018  Opal Kelly’s FrontPanel software is designed to provide controllability and observability for FPGA designs. It’s unique design allows users to describe their own control panels using industry-standard XML descriptions of components such as LEDs, hex displays, push buttons, toggle buttons, triggers, and so on.

Overview

Opal Kelly FrontPanel is a Shareware software in the category Miscellaneous developed by Opal Kelly Incorporated.

The latest version of Opal Kelly FrontPanel is currently unknown. It was initially added to our database on 03/17/2010.

Opal Kelly FrontPanel runs on the following operating systems: Windows.

Opal Kelly FrontPanel has not been rated by our users yet.

• Welcome to Opal Kelly Pins. Sign In or Sign Up. File Downloads Available pin lists. FOMD-ACV-A4; SYZYGY-BRAIN-1.
• FrontPanel is, most importantly, support software for Opal Kelly’s FPGA integration modules. In that role, FrontPanel allows you to quickly and easily download FPGA configuration files via USB or PCI Express to a target device. Once the configuration file is downloaded, the device now takes on that design’s personality and is ready for use.

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A basic example demonstrating use of a Vivado HLS module with the FrontPanelinterface on an XEM7320. For this example a basic FIR filter is implemented inC++ for use with Vivado HLS.

Input data for the FIR filter is transferred from software through a FrontPanelPipeIn endpoint to an input FIFO. This data is then passed through the HLSmodule and transferred to an output FIFO to buffer the output data. This outputdata is read by a FrontPanel PipeOut endpoint and returned to a PC.

Wires and triggers are used to handle the management interface of the HLSmodule.

The HLS FIR filter used in this design is based heavily on the Xilinx HLS FIRfilter example available on github.

Octave

An octave script is provided to generate test data. The test data consists ofan input waveform to the filter and an expected output waveform after passingthrough the filter. Data is provided in both fixed point number format (foruse in hardware) and floating point (for use in the Vivado HLS tools).

To use the octave script, simply run octave gen_data.m.

Note: The data files output from octave must be edited to remove the octavecomments at the top of the files and the blank lines at the end.

Example data is provided in the octave folder.

Vivado HLS Project

Create a new Vivado HLS project according to the instructions below:

• In the Vivado HLS Welcome Page, select Create New project
• Enter an appropriate name and location. Click Next
• Add the HLSfir.cpp file, click 'Browse...' next to 'Top Function' and selectthe fir function as the top level function. Click Next.
• Add the HLSfir_test.cpp file. Click Next.
• Set the Clock Period to 9.92 and select the xc7a75tfgg484-1 part. ClickFinish.

With the new HLS project created, it is possible to run a C simulation,synthesize HDL, and run a C/HDL co-simulation. For the purposes of this example,only synthesis will be performed. Please refer to the Xilinx Vivado HLSdocumentation for more information on C simulation and C/HDL co-simulation.

To synthesize the design, click Solution->Run C Synthesis->Active Solution.

With the design synthesized, export the design by clickingSolution->Export RTL. In the new window, select the 'IP Catalog' format andclick 'OK'. This will create a new Vivado IP repository that can be added toa Vivado hardware project to manage the HLS IP.

Vivado Project

To build this sample design, start a new Vivado project with thexc7a75tfgg484-1 part selected and add the fp_top.v source in the HDLfolder to the project.

With the project created, open the Vivado IP Catalog, right click on'Vivado Repository' and select 'Add Repository'. In the popup window, navigateto the <HLS Project Directory><HLS Project><HLS Solution>implipdirectory and select it. The HLS IP should be added to the Vivado IP Catalog.Select this IP to create an instance of it in the current project.

See the descriptions below for generating the FIFO IP. These parameters arefrom Vivado 2017.4, though later versions should be similar.

With the project created and sources added, simply click the 'GenerateBitstream' button in the Vivado Flow Navigator to build a bitstream.

The result can be found in the Vivado project folder under:

(project name).runs/impl_1/(project name).bit

Ingress FIFO IP

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Instantiate a FIFO Generator IP with the following settings:

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Egress FIFO IP

Instantiate a FIFO Generator IP with the following settings:

Running the sample

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A Python script is provided to demonstrate interaction with the FrontPanelinterface in hardware. This script reads the input data from octave, pipes itto the XEM7320, then reads the filtered data out and writes it to a file. Theoutput data is also compared against the expected output from octave to ensurethat the HLS module performed as expected.

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The sample can be executed with the following command: